`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:13:52 08/23/2012 
// Design Name: 
// Module Name:    Projecto2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Projecto2 (
 clock , // Clock input of the design
 reset , // active high, synchronous Reset input
 clock1hz 
  );
  
 input clock ;
 input reset ;
 output clock1hz;
 reg clock1hz;
 reg [24:0] counter_out ;
   always @(posedge clock)
		if(counter_out==24999999)
			begin
				clock1hz<=~clock1hz;
				counter_out <= 0;
			end
      else if (reset)
			begin	
				clock1hz <= 0; 
				counter_out <= 0;
			end
      else
        counter_out <= counter_out + 1;

 
						
 endmodule 
